Multi-core processors contain multiple processor cores which are connected to an on-die shared cache though a shared cache scheduler and coherence controller. Multi-core multi-processor systems are becoming increasingly popular in commercial server systems because of their improved scalability and modular design. The coherence controller and the shared cache may either be centralized or distributed among the cores depending on the number of cores in the processor design. The shared cache is usually designed as an inclusive cache to provide good snoop filtering.
The internal cores are interconnected by high speed internal buses and the external system bus may be shared among those internal cores and other CMP (chip multiprocessor) resources. To reduce the silicon size and improve the potential performance, the LLC (last level cache) is normally shared by multiple internal cores. However, the CMP system bus and memory controller behavior may not be predictable. They may have burst requests to LLC, such as the external snoop requests. A fixed last level cache access priority could be a benefit for one class of applications and degrade the other class of applications. Thus, a need exists for an architecture that may adaptively adjust the priority and is sensitive to latency.